Electronic Design

Eye-Diagram Analysis Speeds DDR SDRAM Validation

Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...
Business Wire

Non-Volatile Memory Host Controller Interface (NVMHCI) Working Group Announces 1.0 Specification

SANTA CLARA, Calif.--(BUSINESS WIRE)--To further the adoption of NAND flash memory technology in the PC platform for an enhanced user experience, the Non-Volatile Memory Host Controller Interface ...
EDN

Debugging DDR memory interfaces using area-based triggers

DDR bus protocol allows signals to go idle, or tri-state, when they are not active. When debugging or performing JEDEC conformance measurements on the DDR interface, it is often necessary to perform ...
Business Wire

Cypress' HyperBus™ Memory Interface for Instant-on Applications Incorporated into JEDEC xSPI Electrical Interface Standard

SAN JOSE, Calif.--(BUSINESS WIRE)--Cypress Semiconductor Corp. (Nasdaq: CY), a global leader in embedded systems solutions, today announced the inclusion of Cypress' high-bandwidth HyperBus™ 8-bit ...
Design-Reuse

Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2

The emerging DDR3 memory standard will extend the performance range of DDR memories considerably, while maintaining some amount of backwards compatibility with the existing DDR2 memory standard. It is ...
EDN

Implementing an all-digital PHY and delay-locked loop for high-speed DDR2/3 memory interfaces

A high-speed DDR2, DDR2/3, or DDR3 DRAM interface for off-chip memory provides a powerful tool to meet the high-performance demands of new electronic products. However, with advancements come new ...