The era of universal processor architectures is giving way to workload-specific designs optimized for performance, power, and scalability. As data-centric applications in artificial intelligence (AI), ...
The open-source nature of RISC-V brings the benefits of a modular and royalty-free instruction set architecture (ISA) that eliminates licensing fees, can accelerate development, and fosters ...
The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...
The computing industry has reached a significant milestone with the ratification of the 1.0 RISC-V Vector Specification. This development marks the beginning of a new era in computing efficiency, as ...
HANGZHOU, China, January 30, 2026 (EZ Newswire) -- As the global technology industry accelerates its shift toward open architectures and on-device artificial intelligence, Chinese RISC-V chip company ...
Open-Source RISC-V Cores: Analysis Of Scalar and Superscalar Architectures And Out-Of-Order Machines
A new technical paper titled “Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution” was published by researchers at ETH Zurich, Università di ...
BRUSSELS and OTTAWA, Oct. 01, 2024 (GLOBE NEWSWIRE) -- In a joint announcement today, the Eclipse Foundation, one of the world's leading open source software foundations, and OpenHW Group, a global ...
The 2024 RISC-V Summit North America marked a significant milestone for the RISC-V community with the ratification of the RVA23 Profile. This event signifies a major step forward in the evolution of ...
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