The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. To ...
The complicated silicon defect types and defect distribution of new IC manufacturing technologies can result in very low yield for new designs and technology nodes. During technology qualification ...
Design for test (DFT) has been around since the 1960s. The technology was developed to reduce the cost of creating a successful test for an IC. Scan design, fault models, and automatic test pattern ...
SAN MATEO, Calif. — Design-for-test tool vendor SynTest Technologies Inc. is putting the finishing touches on a test-data volume compaction technology for scan-based design. VirtualScan will help ...
Zetacon Corporation designs and manufactures advanced power-control systems in hardware and software. Our products and technologies range from motor drives to power supplies, digital audio with ...
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