EDN

Synopsys Rolls Out Transistor-Level Static Timing Analysis

To address emerging custom circuit design challenges, Mountain View, Calif.-based EDA giant Synopsys Inc. today unveiled its anticipated next-generation transistor-level static timing analysis tool, ...
EDN

Sequence upgrades ShowTime static timing tool

SAN MATEO, Calif. — Sequence Design Inc. has introduced a static timing analysis tool that accounts for inductance delay and IR drop in ASICs and system-on-chip designs. In addition, the company has ...
Semiconductor Engineering

What Happened To Statistical Static Timing Analysis?

About five years ago if you listened to the marketing messages in the EDA industry, you would have thought it would be impossible to produce chips without statistical static timing analysis (SSTA).
Semiconductor Engineering

Closing The Post-Silicon Timing Analysis Gap

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from ...