EDN

Improve top-level simulation strategy for switching DC-DC converters

Just before fabrication, the design flow of all integrated circuits (ICs) culminates in transistor-based, top-level simulations. Unfortunately, verifying functionality, connectivity, and performance ...
Purdue University

Complete atom-by-atom transistor simulation run in 15 minutes

WEST LAFAYETTE, Ind. - A simulation of electrical current moving through a futuristic electronic transistor has been modeled atom-by-atom in less than 15 minutes by Purdue University researchers. The ...
EDN

Taking power analysis to the transistor level for a full chip

Almost every chip being taped out today is mixed-signal in nature. In addition to increased integration of analog and RF blocks, designers are using complex power-management techniques to minimize ...
Business Wire

Magma Acquires ACAD, Introduces FineSim Pro Circuit Simulator; Full-Chip, Tri-Mode Circuit Simulator Enables Simulation of Entire Mixed-Signal SoCs at Transistor Level

SANTA CLARA, Calif.--(BUSINESS WIRE)--July 24, 2006--Magma(R) Design Automation Inc. (Nasdaq:LAVA), a provider of semiconductor design software, today announced the availability of FineSim(R) Pro, the ...
Design-Reuse

The Challenges and Benefits of Analog/Mixed-Signal and RF System Verification above the Transistor Level

Abstract— Today’s on-chip Analog/Mixed-Signal and RF (A/RF) systems have reached a limit of size and complexity where transistor-level SPICE and FastSPICE simulation approaches cannot deliver a ...
WJFW

Innatera Selects Synopsys Simulation to Scale Brain-Inspired Processors for Edge Devices

Innatera adopts Synopsys simulation technology to help design neuromorphic chips that enable low-power AI for wearables, ...
Semiconductor Engineering

Transistor-Level Verification Returns

Technologies that had become specialist tools are moving back into mainstream usage; shift left is not just about doing things earlier in the flow. A few decades ago, all designers did ...
Semiconductor Engineering

Modeling On-Chip Variation At 10/7nm

Timing and variability have long been missing from automated transistor-level simulation tools. At advanced nodes, an update will be required. Simulation, a workhorse tool for semiconductor design, is ...
Design-Reuse

Mixed-Signal Verification Methodology Using Nanosim Integration with VCS

With gate counts and system complexity growing exponentially, new submicron technologies pose many challenges in both the design and verification domains. Nowadays, many high-performance ...
Electronic Design

Identifying transistor-level yield limiters in the FinFET era

As the digital semiconductor manufacturing process moves into the FinFET era, more and more front-end-of-line (FEOL) defects are observed due to extremely small feature size and complex manufacturing ...
Electronic Design

IBIS Modeling (Part 3): How to Achieve a Quality Level 3 IBIS Model via Bench Measurement

The different IBIS quality levels. The steps in the IBIS bench measurement procedure. Process for Quality Level 2a and Level 2b validation. The Input/Output Buffer Information Specification (IBIS) is ...