TechRepublic

FIR Filter Designing using Xilinx System Generator

Digital signal processing techniques are used extensively in a number of applications such as communication and multimedia. DSP functions such as FIR filters and transforms have numerous advantages ...
EDN

How to implement DSP algorithms using the Xilinx Spartan-3E starter board

Editor's Note: This “How To” tutorial is an excerpt from a recently published book: Embedded Design Using Programmable Gate Arrays by Dennis Silage (ISBN-13: 978-1589094864). Dennis is a Professor in ...
EDN

Analyze DSP designs in FPGAs with the z-transform

Crafting DSP algorithms for optimum performance in hardware often requires sophisticated design techniques, such as pipelining and overclocked control logic. Such is the case for implementations using ...
Design-Reuse

Mapping LMS Adaptive Filter IP Core to Multiplier-Array FPGA Architecture for High Channel-Density VOIP Line Echo Cancellation

The LMS adaptive filter is the main functional block in high channel-density line echo cancellers for VOIP. In this paper, we describe an LMS adaptive FIR filter IP and estimate its performance when ...
Hackaday

FIR filter

Digital filters are always an interesting topic, and they are especially attractive with FPGAs. [Pabolo] has been working with them in a series of blog posts. The latest covers an 8th order FIR filter ...
Design-Reuse

Xilinx Spartan-3 Devices Enable High Performance DSP Functions at Breakthrough Low Cost Price Points

Company delivers a 32-channel Viterbi decoder core for communication subsystems for $0.14* and DUC/DDC functions for wireless base stations at $2.22* per channel SAN JOSE, Calif., December 10, 2003 - ...